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stm32f429标准库如何改内部rc时钟工作
- 2022-06-22
参考代码void SystemCoreClockUpdate(void) { uint32_t tmp = 0 pllvco = 0 pllp = 2 pllsource = 0 pllm = 2; #if defined(STM32F446xx) uint32_t pllr = 2; #endif /@@* STM32F446xx */ /@@* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /@@* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x04: /@@* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x08: /@@* PLL P used as system clock source */ /@@* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx) || defined(STM32F469_479xx) if (pllsource != 0) { /@@* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /@@* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } #elif defined(STM32F410xx) || defined(STM32F411xE) #if defined(USE_HSE_BYPASS) if (pllsource != 0) { /@@* HSE used as PLL clock source */ pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } #else if (pllsource == 0) { /@@* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } #endif /@@* USE_HSE_BYPASS */ #endif /@@* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx || STM32F469_479xx */ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; SystemCoreClock = pllvco/pllp; break; #if defined(STM32F446xx) case 0x0C: /@@* PLL R used as system clock source */ /@@* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_R */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /@@* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /@@* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2; SystemCoreClock = pllvco/pllr; break; #endif /@@* STM32F446xx */ default: SystemCoreClock = HSI_VALUE; break; } /@@* Compute HCLK frequency --------------------------------------------------*/ /@@* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /@@* HCLK frequency */ SystemCoreClock >>= tmp; }
