本帖最后由 guyuemao 于 2017-5-1 01:43 编辑
这几天一直因为数码管显示不对而纠结,到底程序错在哪了?
因为想着通过demo设计一个计数器,让数码管动态显示六位数字,之后发现每次显示都是959595,奇了怪了,即使是初始值,也不至于啊!
添加源码如下:
module exp07_demo
(
CLK, RSTn,
Row_Scan_Sig, Column_Scan_Sig
);
input CLK;
input RSTn;
output Row_Scan_Sig;
output Column_Scan_Sig;
/************************************/
parameter T1S = 26'd49_999_999;//50M*1-1=49_999_999
/************************************/
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 26'd0;
else if( Count1 == T1S )
Count1 <= 26'd0;
else
Count1 <= Count1 + 1'b1;
/***************************************/
reg Counter_Sec;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
Counter_Sec <= 20'd111111;
end
else if( Count1 == T1S )
begin
if( Counter_Sec < 20'd999999 ) Counter_Sec <= Counter_Sec + 1'b1;
else Counter_Sec <= 20'd0;
end
/****************************************/
exp07_top U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Number_Data( Counter_Sec ),
.Row_Scan_Sig( Row_Scan_Sig ),
.Column_Scan_Sig( Column_Scan_Sig )
);
/******************************************/
endmodule
分析问题:通过仿真分析程序有没有问题,再查找原因
reg Counter_Sec;
reg Counter_1S;//定义一个1S加法器
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
Counter_Sec <= 20'd123456;
Counter_1S <= 6'd2;
end
else if( Count1 == T1S )
begin
Counter_1S <= Counter_1S+1'b1;
if( Counter_Sec < 20'd999999 ) Counter_Sec <= Counter_Sec + 1'b1;
//if( Counter_Sec < 20'd999999 ) Counter_Sec <=888;
else Counter_Sec <= 20'd888;
end
/****************************************/
定义一个1S加法器Counter_1S,初始值为2,Counter_1S每变化一次值,Counter_Sec以及取模值应该变化,主要是个位变化。
如图:
可以看到Counter_1S=0100时,表示数值变化了两次,个位由6变成了8,与预期符合。
最后发现是红色下载文件导致,删除之后,再选择对应工程文件,OK。
此bug让我纠结了三四天!!!!!
终于可以如愿显示预期的效果了!!!
本帖最后由 guyuemao 于 2017-5-1 01:43 编辑
这几天一直因为数码管显示不对而纠结,到底程序错在哪了?
因为想着通过demo设计一个计数器,让数码管动态显示六位数字,之后发现每次显示都是959595,奇了怪了,即使是初始值,也不至于啊!
添加源码如下:
module exp07_demo
(
CLK, RSTn,
Row_Scan_Sig, Column_Scan_Sig
);
input CLK;
input RSTn;
output Row_Scan_Sig;
output Column_Scan_Sig;
/************************************/
parameter T1S = 26'd49_999_999;//50M*1-1=49_999_999
/************************************/
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 26'd0;
else if( Count1 == T1S )
Count1 <= 26'd0;
else
Count1 <= Count1 + 1'b1;
/***************************************/
reg Counter_Sec;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
Counter_Sec <= 20'd111111;
end
else if( Count1 == T1S )
begin
if( Counter_Sec < 20'd999999 ) Counter_Sec <= Counter_Sec + 1'b1;
else Counter_Sec <= 20'd0;
end
/****************************************/
exp07_top U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Number_Data( Counter_Sec ),
.Row_Scan_Sig( Row_Scan_Sig ),
.Column_Scan_Sig( Column_Scan_Sig )
);
/******************************************/
endmodule
分析问题:通过仿真分析程序有没有问题,再查找原因
reg Counter_Sec;
reg Counter_1S;//定义一个1S加法器
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
begin
Counter_Sec <= 20'd123456;
Counter_1S <= 6'd2;
end
else if( Count1 == T1S )
begin
Counter_1S <= Counter_1S+1'b1;
if( Counter_Sec < 20'd999999 ) Counter_Sec <= Counter_Sec + 1'b1;
//if( Counter_Sec < 20'd999999 ) Counter_Sec <=888;
else Counter_Sec <= 20'd888;
end
/****************************************/
定义一个1S加法器Counter_1S,初始值为2,Counter_1S每变化一次值,Counter_Sec以及取模值应该变化,主要是个位变化。
如图:
可以看到Counter_1S=0100时,表示数值变化了两次,个位由6变成了8,与预期符合。
最后发现是红色下载文件导致,删除之后,再选择对应工程文件,OK。
此bug让我纠结了三四天!!!!!
终于可以如愿显示预期的效果了!!!