FPGA学习之独立按键封装

  • 字符串
  • 开发
  • 实验目的
  • guyuemao
  • LV5工程师
  • |      2017-05-27 09:59:40
  • 浏览量 1237
  • 回复:1
本帖最后由 guyuemao 于 2017-5-27 10:06 编辑 一、实验目的:学习独立按键封装以及多个按键组合 二、实验环境:FPGA开发板AX301,Quartus ii 三、实验介绍:通过按下开发板上的按键,LED灯做出相应的回应。如按下KEY2 ,占空比增加10/255 按下KEY4 ,占空比减小10/255 按下KEY3 ,占空比变为127/255≈50% 四、源码
module key_interface_demo

(

    input CLK,

         input RSTn,

         input Key_In,

         output LED

);



    /******************************************/

    

         wire Key_Out;



    key_interface U1

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),

                  .Key_In( Key_In ),    // input - from top

                  .Key_Out( Key_Out )   // output - to U2

         );



    /******************************************/        

         

         optional_pwm_module U2

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),       

                  .Option_Key( Key_Out ),  // input - from U1

                  .LED( LED )              // output - to top

         );

         

         /******************************************/        



endmodule

module key_interface

(

    input CLK,

         input RSTn,

    input Key_In,

         output Key_Out

);



    // Up Down Left Right Middle

         //key2 up

         //key3 Middle

         //key4 Dwon

         // LED0

         /******************************************/

         

         debounce_module2 U1_Up // Debounded key up

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),

                  .Pin_In( Key_In ),

                  .Pin_Out( Key_Out )

         );

         

         /******************************************/

         

         debounce_module2 U2_Down // Debounded key down

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),

                  .Pin_In( Key_In ),

                  .Pin_Out( Key_Out )

         );

         

        /******************************************/

         

         debounce_module2 U3_Left // Debounded key left

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),

                  .Pin_In( Key_In ),

                  .Pin_Out( Key_Out )

         );

         

        /******************************************/

         

         debounce_module2 U4_Right // Debounded key right

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),

                  .Pin_In( Key_In ),

                  .Pin_Out( Key_Out )

         );

         

         /******************************************/

         

         debounce_module2 U5_Middle // Debounded key middle

         (

             .CLK( CLK ),

                  .RSTn( RSTn ),

                  .Pin_In( Key_In ),

                  .Pin_Out( Key_Out )

         );

         

         /******************************************/



endmodule

module optional_pwm_module

(

    input CLK,

         input RSTn,

         input Option_Key,

         output LED

);

         

         /*******************************/

         

         parameter SEGMENT = 8'd195; // 3.9us 50M*(3.9*e-6)=195

         

         /*******************************/

         

         reg C1;

         

         always @ ( posedge CLK or negedge RSTn )

             if( !RSTn )

                      C1 <= 8'd0;

                  else if( C1 == SEGMENT )

                      C1 <= 8'd0;

                  else 

                      C1 <= C1 + 1'b1; 

                                

         /*******************************/

        

         reg System_Seg;

        

    always @ ( posedge CLK or negedge RSTn )

             if( !RSTn )

                      System_Seg <= 8'd0;

                  else if( System_Seg == 8'd255 )

                      System_Seg <= 8'd0;

                  else if( C1 == SEGMENT )

                      System_Seg <= System_Seg + 1'b1;

        

         /*******************************/

         

         reg Option_Seg;

         

         always @ ( posedge CLK or negedge RSTn )

             if( !RSTn )

                  

                      Option_Seg <= 8'd0;

                                

                  else if( Option_Key ) // Key up = Segment + 10

                  

                      if( Option_Seg < 8'd245) Option_Seg <= Option_Seg + 8'd10; 

                                else Option_Seg <= 8'd255;

                  

                  else if( Option_Key ) // key down = Segment - 10

                  

                      if( Option_Seg > 8'd10) Option_Seg <= Option_Seg - 8'd10; 

                                else Option_Seg <= 8'd0;

                                

                  else if( Option_Key ) // key left = Segment + 1

                  

                      if( Option_Seg < 8'd255) Option_Seg <= Option_Seg + 8'd1; 

                                else Option_Seg <= 8'd255;

                                

                  else if( Option_Key ) // key down = Segment - 1

                  

                      if( Option_Seg > 8'd0) Option_Seg <= Option_Seg - 8'd1; 

                                else Option_Seg <= 8'd0;

                                

                  else if( Option_Key ) // key middle = Segment = half

                  

                                Option_Seg <= 8'd127;

                   

    /******************************************/



    assign LED = ( System_Seg < Option_Seg ) ? 1'b1 : 1'b0;

         

         /******************************************/

         

endmodule



五、RTL图
  • 0
  • 收藏
  • 举报
  • 分享
我来回复

登录后可评论,请 登录注册

所有回答 数量:1
Eagleson 2017-05-27
不错~
0   回复
举报
发布
x
收藏成功!点击 我的收藏 查看收藏的全部帖子