LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY Leijiaqi IS PORT(SAMPLE_CLK,RESET:IN STD_LOGIC; DATA_INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0); RESULT:OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); END Leijiaqi;
ARCHITECTURE BEHAVIOR OF Leijiaqi IS SIGNAL TEMP:STD_LOGIC_VECTOR(47 DOWNTO 0); BEGIN RESULT<=TEMP; PROCESS(SAMPLE_CLK,RESET,DATA_INPUT) BEGIN IF(RESET='1') THEN TEMP<=X"000000000000"; ELSIF(RISING_EDGE(SAMPLE_CLK)) THEN TEMP<=TEMP+DATA_INPUT; END IF; END PROCESS;
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