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  3. 大神帮我看看12232的CPLD程序
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大神帮我看看12232的CPLD程序

蓝蓝的天 2018-06-11 浏览量：626

大神，帮我看看CPLD驱动串行LCD12232的程序，那地方有问题？点不亮。谢谢！

/***********************************************************************
************************* name：LCD12232_Driver *************************
************************* author：made by zzuxzt **************************
************************* time：2014.5.18 ********************************
***********************************************************************/
module lcd12232(input clk      //50M
input rst_n
output reg sdio
output reg sclk
output reg stb
);
 
//--------------------lcd1602 order----------------------------
parameter    BIAS    =  8'h52
RC256  =  8'h30
WDTDIS  =  8'h0a
SYSEN   =  8'h02
LCDON   =  8'h06;



/****************************LCD1602 Driver****************************/  
//-----------------------lcd1602 clk_en---------------------
reg [31:0] cnt;
reg lcd_clk_en;
reg [9:0] state;

always @(posedge clk or negedge rst_n)      
begin 
if(!rst_n)
begin
cnt <= 1'b0;
lcd_clk_en <= 1'b0;
end
else if(cnt == 32'd24999)   //500us
begin 
lcd_clk_en <= 1'b1;
cnt <= 1'b0;
end
else
begin
cnt <= cnt + 1'b1;
lcd_clk_en <= 1'b0;
end
end 

task WriteCmd;
input [7:0] Cmd;
begin
stb <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b1; //Cmd f8  1
#25000 sclk <= 1'b1;  
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b1; //Cmd f8  1
#25000 sclk <= 1'b1;  
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b1; //Cmd f8  1
#25000 sclk <= 1'b1;  
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b1; //Cmd f8  1
#25000 sclk <= 1'b1;  
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b1; //Cmd f8  1
#25000 sclk <= 1'b1;  
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //Cmd f8  0
#25000 sclk <= 1'b1;  
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //Cmd f8  0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //Cmd f8  0
#25000 sclk <= 1'b1;

#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h80)==8'h80)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h40)==8'h40)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h20)==8'h20)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h10)==8'h10)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1; 
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1;

#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h08)==8'h08)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h04)==8'h04)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h02)==8'h02)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   
#25000 if((Cmd&8'h01)==8'h01)
sdio <= 1'b1; //1
else
sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1; 
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;
#25000 sdio <= 1'b0; //30  0
#25000 sclk <= 1'b1;
#25000 stb <= 1'b0;
end
endtask

task WriteData;
input [7:0] Data;
begin
stb <= 1'b1;  
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b1; //1
#25000 sclk <= 1'b1;   
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b1; //1
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b1; //1
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b1; //1
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b1; //1
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b0; //0
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b1; //1
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0;   //0xfa
#25000 sdio <= 1'b0; //0
#25000 sclk <= 1'b1;

#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h80)==8'h80)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h40)==8'h40)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h20)==8'h20)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h10)==8'h10)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;


#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0  
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0  
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0  
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;

#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h08)==8'h08)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h04)==8'h04)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h02)==8'h02)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 
if((Data&8'h01)==8'h01)
sdio <= 1'b1; //1  
else
sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;


#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0  
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0  
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0  
#25000 sclk <= 1'b1;
#25000 sclk <= 1'b0; //0xxx
#25000 sdio <= 1'b0; //0 
#25000 sclk <= 1'b1;

#25000 stb <= 1'b0;
end
endtask

task WriteFF;
begin
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
WriteData(8'hff); 
WriteData(8'hff);
end
endtask

task Write00;
begin
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
WriteData(8'h00); 
WriteData(8'h00);
end
endtask
//-----------------------lcd12232 display state-------------------------------------------

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
state <= 10'd0;

end
else if(lcd_clk_en)     
begin
case(state)
//-------------------init_state---------------------
10'd0: begin                
WriteCmd(8'h30);   
state <= 10'd1;
end

//////////////////////////////////////////
10'd1: begin                
WriteCmd(8'h03);
state <= 10'd2;
end

///////////////////////////////////////////////
10'd2: begin                
WriteCmd(8'h0c);  
state <= 10'd3;
end


10'd3: begin                
WriteCmd(8'h01);   
state <= 10'd4;
end


10'd4: begin                
WriteCmd(8'h06);
state <= 10'd5;
end


////////////////////////画横线
10'd5: begin                
WriteCmd(8'h34);
WriteCmd(8'h36); 
state <= 10'd6;
end

10'd6: begin                
WriteCmd(8'h80);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h81); 
WriteCmd(8'h80); 
Write00;
state <= 10'd7;
end



10'd7: begin                
WriteCmd(8'h82);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h83); 
WriteCmd(8'h80); 
Write00; 
state <= state + 1'd1;
end


10'd8: begin                
WriteCmd(8'h84);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h85); 
WriteCmd(8'h80); 
Write00; 
state <= state + 1'd1;
end

10'd9: begin                
WriteCmd(8'h86);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h87); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd10: begin                
WriteCmd(8'h88);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h89); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd11: begin                
WriteCmd(8'h8A);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h8B); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd12: begin                
WriteCmd(8'h8C);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h8D); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd13: begin                
WriteCmd(8'h8E);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h8F); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end

10'd14: begin                
WriteCmd(8'h90);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h91); 
WriteCmd(8'h80); 
Write00;
state <= 10'd7;
end



10'd15: begin                
WriteCmd(8'h92);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h93); 
WriteCmd(8'h80); 
Write00; 
state <= state + 1'd1;
end


10'd16: begin                
WriteCmd(8'h94);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h95); 
WriteCmd(8'h80); 
Write00; 
state <= state + 1'd1;
end

10'd17: begin                
WriteCmd(8'h96);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h97); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd18: begin                
WriteCmd(8'h98);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h99); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd19: begin                
WriteCmd(8'h9A);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h9B); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd20: begin                
WriteCmd(8'h9C);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h9D); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd21: begin                
WriteCmd(8'h9E);
WriteCmd(8'h80); 
WriteFF;
WriteCmd(8'h9F); 
WriteCmd(8'h80); 
Write00;
state <= state + 1'd1;
end
10'd22: begin
WriteCmd(8'h32);
state <= state + 1'd1;
end
10'd23: begin                
//   
state <= state + 1'd1;
end
10'd24: begin                
//stb <= 1'b1;   

state <= 10'd24;
end
//////////////////////////////////////////////

default: state <= 5'bxxxxx;
endcase
end
end




endmodule
​
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最佳答案

  • 这种大部分是时序的问题了。

    由于FPGA是使用IO来模拟的时序，可能一个不小心就会有一个时序错的。

    你可以使用分析仪抓一下波形看看

    • 发布于 2018-06-19
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其他答案 数量：3
  • 检查屏幕引脚是否接对，尤其gnd，vcc，这两个接上，区域信号线搞错一般显示错乱，很少会不显示
    • 发布于2018-06-12
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  • 代码太长，建议你先删掉一部分，只显示一个字符，看能不能成功
    • 发布于2018-06-12
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  • 第一检查电源，第二检查通信有没有正确，可以上个逻辑分析仪来抓一下波形看看对不对。

    • 发布于2018-06-14
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