Q: When I cleared the interrupt as the last instruction in the ISR the ISR code is called immediately upon exit half the time. Is there a possibility of race condition ?
Answer: The core (Cortex-M3) generates bufferable write transfer. This mean that the CPU consider that the data is written from an AHB point of view while the APB write transfer is managed by the AHB2APB bridge and could be written later. In this case the CPU left the interrupt routine while the interrupt is not yet cleared the CPU will re-enter again on the interrupt handler. To avoid this race condition :
1) ISR routine has to clear the interrupt peripheral flag when just entering in the routine to avoid interrupt missing.
2)ISR routine has to Implement a write to the APB peripheral register ( to clear the peripheral flag) then followed by a read access to the same register/flag. This operation will force the write buffer to complete the effective write and will stall the CPU until the effective write of the bit in the register. Therefore it is independent from the AHB/APB ratio prescaler. Here an example :
STR R1 [R0 #0] ; Store R1 register peripheral register ( or using bit-banding peripheral address)
LDR R2 [R0 #0] ; Load the peipheral register; This will hold the CPU until the effective write of R1.
Use Cortex-M3 Bit-banding feature for interrupt clearing since it is an atomic operation and NVIC pending interrupts will be ignored during this operation however Read-Modify-Write is not.
