分频时钟，作另个模块输入时钟 请教
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myymeimei
- LV0工程师
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| 2013-05-08 20:04:00
- 浏览量 708
- 回复：3
我想把 div分频后的时钟，作为UARTAutomatic 模块的输入时钟，怎么把下面两个模块和到一起呀？
谢谢
module UARTAutomatic
(
Clk,
RSTn,
/*port*/
Rxd,
Txd
);
input Clk ;
input RSTn ;
input Rxd ;
output Txd ;
wire Txd ;
wire SendRequest ;
wire DataIn ;
wire DataOut ;
wire ReceiveByteFinish ;
wire SendByteFinish ;
assign SendRequest = ReceiveByteFinish ;
assign DataIn = DataOut ;
UART UARTEx01
(
.Clk ( Clk ),
.RSTn ( RSTn ),
.Rxd ( Rxd ),
.SendRequest ( SendRequest ),
.DataIn ( DataIn ),
.Txd ( Txd ),
.DataOut ( DataOut ),
.ReceiveByteFinish ( ReceiveByteFinish ),
.SendByteFinish ( SendByteFinish )
);
endmodule
// 分频
module div(Clk,clkout);
input Clk;
output reg clkout;
reg count;
always@(posedge Clk) begin
if(count==27) begin
count<=0;
clkout<=~clkout;
end
else begin
count<=count+1;
clkout<=clkout;
end
end
endmodule
新人，目前水平，点灯阶段...
我想把 div分频后的时钟，作为UARTAutomatic 模块的输入时钟，怎么把下面两个模块和到一起呀？
谢谢
module UARTAutomatic
(
Clk,
RSTn,
/*port*/
Rxd,
Txd
);
input Clk ;
input RSTn ;
input Rxd ;
output Txd ;
wire Txd ;
wire SendRequest ;
wire DataIn ;
wire DataOut ;
wire ReceiveByteFinish ;
wire SendByteFinish ;
assign SendRequest = ReceiveByteFinish ;
assign DataIn = DataOut ;
UART UARTEx01
(
.Clk ( Clk ),
.RSTn ( RSTn ),
.Rxd ( Rxd ),
.SendRequest ( SendRequest ),
.DataIn ( DataIn ),
.Txd ( Txd ),
.DataOut ( DataOut ),
.ReceiveByteFinish ( ReceiveByteFinish ),
.SendByteFinish ( SendByteFinish )
);
endmodule
// 分频
module div(Clk,clkout);
input Clk;
output reg clkout;
reg count;
always@(posedge Clk) begin
if(count==27) begin
count<=0;
clkout<=~clkout;
end
else begin
count<=count+1;
clkout<=clkout;
end
end
endmodule
新人，目前水平，点灯阶段...
11
2013-05-08
dxzdxz
2013-05-08
