本帖最后由 guyuemao 于 2017-4-16 21:23 编辑
最近把很多年前买的FPGA开发板找出来了，开始学习FPGA,希望这一次可以坚持下来，特此立贴。
实验目的：实现一个LED灯不断闪烁，另外三个led灯如流水灯循环点亮。
实验环境：FPGA开发板AX301,Quartus ii
实验介绍介绍：
源码：
module blink_module
( CLK, RSTn, Blink_led_Out);
input CLK;
input RSTn;
output Blink_led_Out;
parameter T100MS = 23'd5_000_000;//DB4CE15开发板使用的晶振为50MHz，50M*0.01=5_000_000
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 23'd0;
else if( Count1 == T100MS )
Count1 <= 23'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 23'd2_500_000 && Count1 < 23'd5_000_000 )//
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign Blink_led_Out = rLED_Out;
/***************************************/
endmodule
module mix_module
(
CLK, RSTn, Blink_led,run_led
);
input CLK;
input RSTn;
output Blink_led;
outputrun_led;
wire Blink_led;
blink_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Blink_led_Out( Blink_led )
);
wire run_led;
run_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( run_led )
);
assign Blink_led=Blink_led;
assign run_led=run_led;
endmodule
module run_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
parameter T100MS = 23'd5_000_000;//DB4CE15开发板使用的晶振为50MHz，50M*0.01=5_000_000
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 23'd0;
else if( Count1 == T100MS )
Count1 <= 23'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 3'b001;
else if( Count1 >= 23'd5_000_000 )//
begin
if( rLED_Out == 3'b000)
rLED_Out <= 3'b001;
else
rLED_Out <= { rLED_Out, 1'b0 };
end
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
流水灯源码修改之后效果一样：
module run_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
parameter T100MS = 23'd5_000_000;//DB4CE15开发板使用的晶振为50MHz，50M*0.01=5_000_000
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 23'd0;
else if( Count1 == T100MS )
Count1 <= 23'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 3'b001;
else if( Count1 >= 23'd5_000_000 )//100ms的第一个四分之一，具体请看教程11页的图2.1C
// begin
// if( rLED_Out == 3'b000)
// rLED_Out <= 3'b001;
// else
//rLED_Out <= { rLED_Out, 1'b0 };
rLED_Out <= {rLED_Out, rLED_Out};
// end
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
本帖最后由 guyuemao 于 2017-4-16 21:23 编辑
最近把很多年前买的FPGA开发板找出来了，开始学习FPGA,希望这一次可以坚持下来，特此立贴。
实验目的：实现一个LED灯不断闪烁，另外三个led灯如流水灯循环点亮。
实验环境：FPGA开发板AX301,Quartus ii
实验介绍介绍：
源码：
module blink_module
( CLK, RSTn, Blink_led_Out);
input CLK;
input RSTn;
output Blink_led_Out;
parameter T100MS = 23'd5_000_000;//DB4CE15开发板使用的晶振为50MHz，50M*0.01=5_000_000
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 23'd0;
else if( Count1 == T100MS )
Count1 <= 23'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 23'd2_500_000 && Count1 < 23'd5_000_000 )//
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign Blink_led_Out = rLED_Out;
/***************************************/
endmodule
module mix_module
(
CLK, RSTn, Blink_led,run_led
);
input CLK;
input RSTn;
output Blink_led;
outputrun_led;
wire Blink_led;
blink_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.Blink_led_Out( Blink_led )
);
wire run_led;
run_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( run_led )
);
assign Blink_led=Blink_led;
assign run_led=run_led;
endmodule
module run_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
parameter T100MS = 23'd5_000_000;//DB4CE15开发板使用的晶振为50MHz，50M*0.01=5_000_000
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 23'd0;
else if( Count1 == T100MS )
Count1 <= 23'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 3'b001;
else if( Count1 >= 23'd5_000_000 )//
begin
if( rLED_Out == 3'b000)
rLED_Out <= 3'b001;
else
rLED_Out <= { rLED_Out, 1'b0 };
end
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
流水灯源码修改之后效果一样：
module run_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
parameter T100MS = 23'd5_000_000;//DB4CE15开发板使用的晶振为50MHz，50M*0.01=5_000_000
reg Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 23'd0;
else if( Count1 == T100MS )
Count1 <= 23'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 3'b001;
else if( Count1 >= 23'd5_000_000 )//100ms的第一个四分之一，具体请看教程11页的图2.1C
// begin
// if( rLED_Out == 3'b000)
// rLED_Out <= 3'b001;
// else
//rLED_Out <= { rLED_Out, 1'b0 };
rLED_Out <= {rLED_Out, rLED_Out};
// end
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
源码：
Eagleson
2017-04-17
qq1328512480
2017-04-17
guyuemao
回复
2017-04-17
安卓小王子
回复
2017-04-20
