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- 河北省
- 单片机 FPGA/CPLD
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vhdl的ram的读写
- 2018-08-29
data_out对应ram的输入，wradd为写地址，rcmd1为写使能，rdress为写地址。same表示写进去的数据等于读出来的数据，但是same一直为0，是没读进去么，为什么，我写了两边呢？？？
stm32的FSMC读写sram
- 2018-08-20
rd是我给的外部中断，上升沿有效；oe是sram的输出使能，低电平有效。理论上应该rd有三个上升沿，oe有三个下降沿，然后串口输出6个数据。但是通过示波器看rd和oe的波形，结果不对，这是为什么？是fmc读sram的是将较长，中断已经完成，sram还没读完么？？？？
quartus里输出有波形，modelsim输出没波形
- 2018-08-17
vhd文件：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rxd is generic(data_bits:integer:=8); port(bclk_inrxd_in:in std_logic; rx_done:out std_logic; rx_buffer:out std_logic_vector(7 downto 0));end rxd;architecture beheavior of rxd istype states is(r_noner_startr_centerr_waitr_sampler_stop);signal state:states:=r_none;signal rxd_sync:std_logic;begin process(rxd_in) begin if rxd_in='0' then rxd_sync<='0'; else rxd_sync<='1'; end if; end process; process(bclk_inrxd_sync) variable count:std_logic_vector(3 downto 0); variable r_cnt:integer:=0; variable buf:std_logic_vector(7 downto 0); begin if bclk_in'event and bclk_in='1' then case state is when r_none=> if count="1110" then state<=r_start; rx_done<='0'; count:="0000"; else count:=count+1; state<=r_none; end if; when r_start=> if rxd_sync='0' then state<=r_center; else state<=r_start; end if; when r_center=> if rxd_sync='0' then if count="0100"then --排除噪音的干扰 state<=r_wait; count:="0000"; else count:=count+'1'; state<=r_center; end if; else state<=r_start; end if; when r_wait=> if count="1110" then --数据位和奇偶校验位将每隔16个bclk周期被采样一次（即每一个波特率时钟被采样一次） if r_cnt=data_bits then state<=r_stop; else state<=r_sample; end if; count:="0000"; --等待计数到15个bclk，在16个bclk进入R_SAMPLE状态进行数据位的采样检测 else count:=count+'1'; state<=r_wait; end if; when r_sample=> buf(r_cnt):=rxd_sync; --接收发送数据 r_cnt:=r_cnt+1; state<=r_wait; when r_stop=> r_cnt:=0; rx_buffer<=buf; rx_done<='1'; state<=r_none; when others=> state<=r_none; end case; end if; end process;end beheavior;tb文件：LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY rxd_vhd_vec_tst ISEND rxd_vhd_vec_tst;ARCHITECTURE rxd_arch OF rxd_vhd_vec_tst IS-- constants -- signals SIGNAL bclk_in : STD_LOGIC;SIGNAL rx_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL rx_done : STD_LOGIC;SIGNAL rxd_in : STD_LOGIC;COMPONENT rxd PORT ( bclk_in : IN STD_LOGIC; rx_buffer : out STD_LOGIC_VECTOR(7 DOWNTO 0); rx_done : out STD_LOGIC; rxd_in : IN STD_LOGIC );END COMPONENT;BEGIN i1 : rxd PORT MAP (-- list connections between master ports and signals bclk_in => bclk_in rx_buffer => rx_buffer rx_done => rx_done rxd_in => rxd_in );-- bclk_int_prcs_bclk_in: PROCESSBEGINLOOP bclk_in <= '0'; WAIT FOR 500 ps; bclk_in <= '1'; WAIT FOR 500 ps; IF (NOW >= 10000000 ps) THEN WAIT; END IF;END LOOP;END PROCESS t_prcs_bclk_in;-- rxd_int_prcs_rxd_in: PROCESSBEGINLOOP rxd_in <= '0'; WAIT FOR 10000 ps; rxd_in <= '1'; WAIT FOR 10000 ps; IF (NOW >= 10000000 ps) THEN WAIT; END IF;END LOOP;END PROCESS t_prcs_rxd_in;END rxd_arch;