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FPGA1驱动MAX7219的问题

蓝蓝的天 2018-05-09 浏览量：1352

先上程序：

module max7219(clkrst_nclk1loaddin);
input clkrst_n;
output clk1loaddin;

//reg[11:0] cnt;
reg[11:0] cnt1;

always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt1 <= 0;


else if(cnt1==12'd2560)
cnt1 <= 0;

else cnt1 <= cnt1+1'b1;

reg clk1_rdin_r;
function Write_Max7219_byte;
input [7:0] byte;


//always @(negedge clk1)
begin
case(cnt1)
12'd0:
begin
clk1_r=0;
din_r=byte[7];
clk1_r=1;
end
12'd320:
begin
clk1_r=0;
din_r=byte[6];
clk1_r=1;
end

12'd640:
begin
clk1_r=0;
din_r=byte[5];
clk1_r=1;
end

12'd960:
begin
clk1_r=0;
din_r=byte[4];
clk1_r=1;
end
12'd1280:
begin
clk1_r=0;
din_r=byte[3];
clk1_r=1;
end
12'd1600:
begin
clk1_r=0;
din_r=byte[2];
clk1_r=1;
end
12'd1920:
begin
clk1_r=0;
din_r=byte[1];
clk1_r=1;
end
12'd2240:
begin
clk1_r=0;
din_r=byte[0];
clk1_r=1;
end

endcase
end
endfunction

assign clk1=clk1_r;
assign din=din_r;

reg load_r;

function Write_Max7219;
input [7:0] addr;
input [7:0] dat;
reg ab;
//always @(posedge clk or negedge rst_n)
begin
//load_r<=1'b0;
a=Write_Max7219_byte(addr);
b=Write_Max7219_byte(dat);
//load_r=1'b1;
end
endfunction
assign load=load_r;

reg a;
always @(posedge clk)

begin
load_r<=1'b0;
//a=Write_Max7219(SHUT_DOWN 8'd1); //Normal Operation XXXXXXX1 Shutdown Mode XXXXXXXX0
a=Write_Max7219(8'hc 8'd1);
a=Write_Max7219(8'hf 8'd0); //Normal Operation XXXXXXX0 Display Test Mode

   a=Write_Max7219(8'h9 8'hff); //Decode Mode Select D7~D0 1 B decode 0 No decode
   a=Write_Max7219(8'hb 8'd4); //SCAN LIMIT 0~7 0xX0~0xX7
   a=Write_Max7219(8'ha 8'd4); //Set Intensity 0xX0~0xXf
   a=Write_Max7219(11);
   a=Write_Max7219(22);
   a=Write_Max7219(38);
   a=Write_Max7219(46);
load_r<=1'b1;
end
endmodule

我写了个FPGA驱动MAX7219的程序，下载进去以后，本来四个
数码管应该显示1286的，可是要么全亮，要么不亮。
请大神看看，哪里有问题呀？谢谢！

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