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- 河北省
- 单片机 FPGA/CPLD
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fpga实现串口接收模块
- 2018-10-30
我用fpga写了一个串口接收模块，但是有时候接收时数据会发生错误，希望大家帮我看看代码，是哪儿的错误？？？ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity rxd is generic(data_bits:integer:=8); port(bclk_inrxd_in:in std_logic; rx_done:out std_logic; rx_buffer:out std_logic_vector(7 downto 0)); end rxd; architecture beheavior of rxd is type states is(r_startr_centerr_waitr_sampler_stop); signal state:states:=r_start; signal rxd_sync:std_logic; signal rxd_fall:std_logic; begin process(bclk_in) begin if bclk_in'event and bclk_in='1' then rxd_sync<=rxd_in; if(rxd_sync='1' and rxd_in='0')then rxd_fall<='1'; else rxd_fall<='0'; end if; end if; end process; process(bclk_inrxd_in) variable count:std_logic_vector(3 downto 0); variable r_cnt:integer:=0; variable buf:std_logic_vector(7 downto 0); begin if bclk_in'event and bclk_in='1' then case state is when r_start=> if rxd_fall='1' then state<=r_center; rx_done<='0'; r_cnt:=0; else state<=r_start; rx_done<='0'; end if; when r_center=> if rxd_in='0' then if count="1001"then --排除噪音的干扰 state<=r_wait; count:="0000"; else count:=count+'1'; state<=r_center; end if; else state<=r_start; end if; when r_wait=> if count="1110" then --数据位和奇偶校验位将每隔16个bclk周期被采样一次（即每一个波特率时钟被采样一次） if r_cnt=data_bits then state<=r_stop; else state<=r_sample; end if; count:="0000"; --等待计数到15个bclk，在16个bclk进入R_SAMPLE状态进行数据位的采样检测 else count:=count+'1'; state<=r_wait; end if; when r_sample=> buf(r_cnt):=rxd_in; --接收发送数据 r_cnt:=r_cnt+1; state<=r_wait; when r_stop=> if rxd_in='1' then rx_buffer<=buf; rx_done<='1'; state<=r_start; else state<=r_start; end if; when others=> state<=r_start; end case; end if; end process; end beheavior;
nios软核的生成
- 2018-10-19
Error (204012): Can't generate netlist output files because the file "D:/VHDL/nios/lcdcore/synthesis/submodules/lcdcore_nios2_gen2_0_cpu.v" is an OpenCore Plus time-limited file. Remove the unlicensed cores or obtain a license for those OpenCore Plus time-limited IP cores used in the design. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.Error (204009): Can't generate netlist output files because the license for encrypted file "D:/VHDL/nios/lcdcore/synthesis/submodules/lcdcore_nios2_gen2_0_cpu.v" is not available我配置完qsy之后，将原理图进行编译的时候出现这两类错误，这是哪儿的原因？？？？