LCMXO2-1200HC-4TG100I 有没有可以替代或者性能更好的 FPGA?
在使用vivado对ip使用ooc进行综合一直会报:[Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'mb_system/mb_system/microblaze_0_local_memory/lmb_bram' at clock pin 'clka' is different from the actual clock period '10.000' this can lead to different synthesis results.我如何在ip生成过程给他们指定时钟频率呢?
如上图所示的X1Y8,生成一个IP那么这个是固定的,而我需要实例化4个,并且分别为x1y8 x1y12 x0y12和x0y16。如何可以我只添加一个ip实现?
vhd文件:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rxd is generic(data_bits:integer:=8); port(bclk_inrxd_in:in std_logic; rx_done:out std_logic; rx_buffer:out std_logic_vector(7 downto 0));end rxd;architecture beheavior of rxd istype states is(r_noner_startr_centerr_waitr_sampler_stop);signal state:states:=r_none;signal rxd_sync:std_logic;begin process(rxd_in) begin if rxd_in='0' then rxd_sync<='0'; else rxd_sync<='1'; end if; end process; process(bclk_inrxd_sync) variable count:std_logic_vector(3 downto 0); variable r_cnt:integer:=0; variable buf:std_logic_vector(7 downto 0); begin if bclk_in'event and bclk_in='1' then case state is when r_none=> if count="1110" then state<=r_start; rx_done<='0'; count:="0000"; else count:=count+1; state<=r_none; end if; when r_start=> if rxd_sync='0' then state<=r_center; else state<=r_start; end if; when r_center=> if rxd_sync='0' then if count="0100"then --排除噪音的干扰 state<=r_wait; count:="0000"; else count:=count+'1'; state<=r_center; end if; else state<=r_start; end if; when r_wait=> if count="1110" then --数据位和奇偶校验位将每隔16个bclk周期被采样一次(即每一个波特率时钟被采样一次) if r_cnt=data_bits then state<=r_stop; else state<=r_sample; end if; count:="0000"; --等待计数到15个bclk,在16个bclk进入R_SAMPLE状态进行数据位的采样检测 else count:=count+'1'; state<=r_wait; end if; when r_sample=> buf(r_cnt):=rxd_sync; --接收发送数据 r_cnt:=r_cnt+1; state<=r_wait; when r_stop=> r_cnt:=0; rx_buffer<=buf; rx_done<='1'; state<=r_none; when others=> state<=r_none; end case; end if; end process;end beheavior;tb文件:LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY rxd_vhd_vec_tst ISEND rxd_vhd_vec_tst;ARCHITECTURE rxd_arch OF rxd_vhd_vec_tst IS-- constants -- signals SIGNAL bclk_in : STD_LOGIC;SIGNAL rx_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL rx_done : STD_LOGIC;SIGNAL rxd_in : STD_LOGIC;COMPONENT rxd PORT ( bclk_in : IN STD_LOGIC; rx_buffer : out STD_LOGIC_VECTOR(7 DOWNTO 0); rx_done : out STD_LOGIC; rxd_in : IN STD_LOGIC );END COMPONENT;BEGIN i1 : rxd PORT MAP (-- list connections between master ports and signals bclk_in => bclk_in rx_buffer => rx_buffer rx_done => rx_done rxd_in => rxd_in );-- bclk_int_prcs_bclk_in: PROCESSBEGINLOOP bclk_in <= '0'; WAIT FOR 500 ps; bclk_in <= '1'; WAIT FOR 500 ps; IF (NOW >= 10000000 ps) THEN WAIT; END IF;END LOOP;END PROCESS t_prcs_bclk_in;-- rxd_int_prcs_rxd_in: PROCESSBEGINLOOP rxd_in <= '0'; WAIT FOR 10000 ps; rxd_in <= '1'; WAIT FOR 10000 ps; IF (NOW >= 10000000 ps) THEN WAIT; END IF;END LOOP;END PROCESS t_prcs_rxd_in;END rxd_arch;
fifo是我用IP核生成的,data_out对应FIFO的写入数据,wrcmd对应FIFO的写使能;rdcmd对应FIFO的读使能;data_in对应FIFO的输出数据;我使能rcmd,通过仿真发现FIFO里面没有数据。
当我的发送使能三个tcmd和ccmd同时来的时候,数据发送一直不对,试了好多方法,但是不管用,谁能帮我看看,写一下改的程序,谢谢
做zynq的FSBL前,我在vivado内创建硬件平台,从板子的原理上看到ps的bank500的BANK io电压是1.8V,而如果我在vivado内的zynq process system内配置为3.3V,如下图所示:那么bank500的io输出高电平电压是多少,输入低电平电压是多少,输入检测电压在什么范围内为高,又在什么范围内检测为低呢?
如题,我通过SDK烧录QSPI,给zynq重新上电后,qspi打印了FSBL的log,这表明bootrom已经成功读取到QSPI的数据并拷贝到ps ram内,且移交到FSBL代码,但是FSBL在读取QSPI ID时打印出了3F FF FF,这明显不对,之后qspi读取application的offset,却读到FFFF57FF,之后DATA ABORT HANDLE,fsbl自动软重启,之后停留在Partition Count: 14Invalid Partition CountPartition Header Load FailedFSBL Status = 0xA00E这个log,很郁闷啊?这怎么解决,fsbl没法移交到application。
ALTERA FPGA直接操作PHY芯片,然后数据转换成串流,有好的方案没?主要是考虑到速度。所以没有使用niosII。看下有大神简单提供下思路