Quartus II 仿真验证时出现以下错误如何处理?Info: Starting Nativelink simulation with ModelSim-Altera softwareSourced Nativelink script c:/altera/13.0/quartus/common/tcl/internal/nativelink/modelsim.tclWarning: File rs232_run_msim_rtl_verilog.do already exists - backing up current file as rs232_run_msim_rtl_verilog.do.bak2error deleting "msim_transcript": permission deniedError: Nativelink simulation flow was NOT successful
vhd文件:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rxd is generic(data_bits:integer:=8); port(bclk_inrxd_in:in std_logic; rx_done:out std_logic; rx_buffer:out std_logic_vector(7 downto 0));end rxd;architecture beheavior of rxd istype states is(r_noner_startr_centerr_waitr_sampler_stop);signal state:states:=r_none;signal rxd_sync:std_logic;begin process(rxd_in) begin if rxd_in='0' then rxd_sync<='0'; else rxd_sync<='1'; end if; end process; process(bclk_inrxd_sync) variable count:std_logic_vector(3 downto 0); variable r_cnt:integer:=0; variable buf:std_logic_vector(7 downto 0); begin if bclk_in'event and bclk_in='1' then case state is when r_none=> if count="1110" then state<=r_start; rx_done<='0'; count:="0000"; else count:=count+1; state<=r_none; end if; when r_start=> if rxd_sync='0' then state<=r_center; else state<=r_start; end if; when r_center=> if rxd_sync='0' then if count="0100"then --排除噪音的干扰 state<=r_wait; count:="0000"; else count:=count+'1'; state<=r_center; end if; else state<=r_start; end if; when r_wait=> if count="1110" then --数据位和奇偶校验位将每隔16个bclk周期被采样一次(即每一个波特率时钟被采样一次) if r_cnt=data_bits then state<=r_stop; else state<=r_sample; end if; count:="0000"; --等待计数到15个bclk,在16个bclk进入R_SAMPLE状态进行数据位的采样检测 else count:=count+'1'; state<=r_wait; end if; when r_sample=> buf(r_cnt):=rxd_sync; --接收发送数据 r_cnt:=r_cnt+1; state<=r_wait; when r_stop=> r_cnt:=0; rx_buffer<=buf; rx_done<='1'; state<=r_none; when others=> state<=r_none; end case; end if; end process;end beheavior;tb文件:LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY rxd_vhd_vec_tst ISEND rxd_vhd_vec_tst;ARCHITECTURE rxd_arch OF rxd_vhd_vec_tst IS-- constants -- signals SIGNAL bclk_in : STD_LOGIC;SIGNAL rx_buffer : STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL rx_done : STD_LOGIC;SIGNAL rxd_in : STD_LOGIC;COMPONENT rxd PORT ( bclk_in : IN STD_LOGIC; rx_buffer : out STD_LOGIC_VECTOR(7 DOWNTO 0); rx_done : out STD_LOGIC; rxd_in : IN STD_LOGIC );END COMPONENT;BEGIN i1 : rxd PORT MAP (-- list connections between master ports and signals bclk_in => bclk_in rx_buffer => rx_buffer rx_done => rx_done rxd_in => rxd_in );-- bclk_int_prcs_bclk_in: PROCESSBEGINLOOP bclk_in <= '0'; WAIT FOR 500 ps; bclk_in <= '1'; WAIT FOR 500 ps; IF (NOW >= 10000000 ps) THEN WAIT; END IF;END LOOP;END PROCESS t_prcs_bclk_in;-- rxd_int_prcs_rxd_in: PROCESSBEGINLOOP rxd_in <= '0'; WAIT FOR 10000 ps; rxd_in <= '1'; WAIT FOR 10000 ps; IF (NOW >= 10000000 ps) THEN WAIT; END IF;END LOOP;END PROCESS t_prcs_rxd_in;END rxd_arch;
fifo是我用IP核生成的,data_out对应FIFO的写入数据,wrcmd对应FIFO的写使能;rdcmd对应FIFO的读使能;data_in对应FIFO的输出数据;我使能rcmd,通过仿真发现FIFO里面没有数据。
画了个cyclone iv的最小系统,但是用JTAG下载时一直出现“unable to scan device chain”,这是哪儿的原因????
延时程序,empty对应FIFO的空标志位,如果tcmd2和tcmd3同时来,我给两个延时,这样两个数据都可以存入FIFO。data_out对应FIFO的写入数据;rcmd对应FIFO的写使能;datalength对应FIFO的读使能;data_in对应FIFO的输出数据;最后还是只能读出一个数据,这是为什么?
编译uart_ram_VGA例程时,出现上述错误,应该是缺少了文件,哪里可以找到这两文件呢?
当我串口调试助手打开了,quartus就扫描不到USB blaster,但是关闭之后就能扫描到,这应该怎么办???设备管理器:下面三张图分别是同时插上USB blaster和串口,,拔掉串口,,拔掉USB blaster
case(data/8) 8'h0: key = 1; 8'h1: key = 2;这样写data/8能得到整数,实现case语句吗?
当我的发送使能三个tcmd和ccmd同时来的时候,数据发送一直不对,试了好多方法,但是不管用,谁能帮我看看,写一下改的程序,谢谢
每次电脑刚开机quartus能检测到usb blaster,当我在打开烧录软件,就检测不到了。然后重启后又能检测到一次,之后有检测不到。altera jtag serve正常启动,它的可执行文件路径也正确,就是检测不到,为什么?
对于ARM Cortex M和ARM Cortex A都有一定了解了,想学习FPGA,有没有好的入门教程。
我只发了一个数据,然后数据存储到fifo里,datalength+1,但是最后发出两个数据是哪儿的原因???还有rcmd1单次触发的波形